module Forward(
    input [4:0] rt_from_ID_EX, rs_from_ID_EX,
    input [4:0] rd_from_EX_MEM, rd_from_MEM_WB,
    input EX_MEM_RegWrite, MEM_WB_RegWrite,
    output reg [1:0] ForwardA, ForwardB
);

wire EXDectA,MEMDectA,EXDectB,MEMDectB;
// forward A
assign EXDectA = EX_MEM_RegWrite 
                & (rd_from_EX_MEM!=5'd0)
                & (rd_from_EX_MEM == rs_from_ID_EX);
assign MEMDectA = MEM_WB_RegWrite 
                & (rd_from_MEM_WB != 5'd0)
                & (~EXDectA) 
                &(rd_from_MEM_WB==rs_from_ID_EX);
// forward B
assign EXDectB = EX_MEM_RegWrite 
                & (rd_from_EX_MEM!=5'd0)
                & (rd_from_EX_MEM == rt_from_ID_EX);
assign MEMDectB = MEM_WB_RegWrite 
                & (rd_from_MEM_WB != 5'd0)
                & (~EXDectB) 
                &(rd_from_MEM_WB==rt_from_ID_EX);

always@(*)begin
    if(EXDectA)begin
           ForwardA <= 2'b10;
    end
    else if(MEMDectA)begin
        ForwardA <= 2'b01;
    end 
    else ForwardA <= 2'b00;
end

always@(*)begin
    if(EXDectB)begin
           ForwardB <= 2'b10;
    end
    else if(MEMDectB)begin
        ForwardB <= 2'b01;
    end 
    else ForwardB <= 2'b00;
end
endmodule